In the semiconductor industry, there is a need to deposit materials across areas of vastly differing topography. On a single workpiece, there may be a need for deposition of insulative material into a shallow trench providing isolation for a transistor which additionally requires alloyed contacts to be deposited into high aspect ratio vias and further requires continuous pure metal contacts through multiple levels of insulator material. Deposition techniques of chemical vapor deposition (CVD), evaporation and sputtering are well established in the industry. However, as discussed in detail below, no single deposition technique is workable for all of the industry needs. Nor are the well-known techniques usable or extendable to the dimensional requirements of the leading edge of the technology.
Specifically, in multilevel metallurgy processing, there is a need to deposit conductors into high aspect ratio trenches in the dielectric layers. In the past, a so-called "cloisonne" approach was used wherein blanket metal was deposited and patterned by reactive ion etching, followed by deposition of the dielectric material over, and between, the metal features, and finally, polishing of the overlying dielectric material to reveal the metal. A similar embodiment of the cloisonne approach is to deposit the metal through a lift-off pattern, as is well-known in the semiconductor art, and proceeding to deposit the dielectric as above. The lift-off and standard cloisonne processes are functional for processing layers having large features. However, as the patterned metal features become finer, it is virtually impossible to perform liftoff without removing the desired metal features along with the overlying metal or resist. Furthermore, overcoating with the dielectric frequently causes breaking, or at least bending of the fine metal lines or studs. The foregoing difficulties indicate the need for a major processing shift. Future technological requirements also include a switch from the currently preferred metallurgy of aluminum to copper, which is a softer metal more prone to distortion under pressure. The standard, reactive ion etching (RIE) method for patterning of the blanket metal in cloisonne processing cannot be practiced with Cu, since there are no volatile decomposition products of Cu. The alternative deposition liftoff techniques are also limited in applicability in a copper structure given the susceptibility of copper to corrosion by the lift-off solvents. Therefore, a cloisonne replacement process must address not only the dimensional tolerances needed for the advanced technology but also the material requirements.
A so-called "damascene" process flow has been developed to replace the cloisonne techniques of the past. The damascene process, as is taught and claimed in U.S. Pat. No. 4,702,792 of Chow, et al, assigned to the present assignee, the teachings of which are herein incorporated by reference, includes the following basic process flow: a dielectric material is blanket deposited onto the substrate; the dielectric material is patterned to form openings; conductive material is deposited onto the substrate in sufficient thickness to fill the openings; and excess conductive material is removed from the surface of the dielectric by means of a chemical or mechanical, or combined chemical-mechanical polishing technique. Deposition techniques currently in use and taught in the literature include conformal coating techniques such as CVD and sputtering. Drawbacks associated with CVD include the creation of voids in the center of the filled opening due to the conformal nature of the deposition method, particularly in the instance of high aspect ratio features. With sputtering, it is impossible to achieve a complete fill, particularly along the sidewalls of high aspect ratio openings. Evaporation is successful in covering shallow features; but, is generally not practical for the filling of high aspect ratio features.
The teachings of Chow, et al not only provide an alternative technique to the cloisonne approach of substrate processing, but also discuss the use of polymeric materials as the dielectric for electronic devices. The Chow, et al patent teaches the use of a polymeric material as the patterned dielectric which may remain in place after metal deposition and polishing to serve as the dielectric material; or, may be removed and subsequently replaced by glass or another suitable dielectric. Polymeric materials are desirable for a number of reasons, such as cost, materials characteristics, etc. But, the use of polymers does compound the processing difficulties given the stringent temperature constraints associated with polymers. CVD cannot, typically, be utilized with the relatively low temperature polymeric insulators. Likewise, sputtering cannot be utilized with a polymeric layer wherein the dielectric itself could be damaged by the sputtering process.
The multilevel metallization (so-called back-end-of-the-line) processing, which has been described at length heretofore, calls for a lower level of finesse than is required in the formation of the underlying transistor structure itself where chemical-mechanical polishing is not as option. Greater control, both mechanical and thermal, is required when depositing materials such as silicon for isolation trenches or metal alloys for transistor contacts. Isolation trenches have become more difficult to fill given the increasingly shallow profiles of devices. Laser ablation of silicon has been proposed in the art (see, e.g. "Laser-induced Plasmas for Primary Ion Deposition of Epitaxial Ge and Si Films", D. Lubben, et al, Journal Vac. Sci. Tech., Volume B, No. 3, p. 968 (1985)); however, for fine (either narrow and deep, or shallow) features, the technique has proven to be too unrefined. Large silicon particles, or "spits", are deposited leading to incomplete fill in the case of high aspect ratio features and low density, non-planar fill in the case of shallow features. An accurate method for providing atomic silicon to prescribed surfaces is, therefore, needed.
With respect to contact formation, it may be desirable to achieve graded or alloyed interfaces on the doped polysilicon. In addition to the dimensional requirements, it is imperative to operate at sufficiently low temperatures to prevent diffusion of the dopant from the underlying polysilicon into the contact material. CVD cannot be utilized to deposit alloys where graded interfaces are desired. Moreover, typical CVD operating temperatures are excessive where diffusion is concerned. Sputtering can provide alloys, however, as noted above, it is impossible to achieve a complete fill of fine features with sputtering.
Ideally, the apparently disparate processing requirements set forth above can be addressed wherein a single deposition technique can be employed in the various stages of semiconductor device processing. It may be further desired to minimize tooling by thereby employing a single deposition chamber for the various processing steps.
It is, therefore, an objective of the present invention to provide a method for achieving a complete fill of a high aspect ratio feature.
It is another objective of the present invention to provide metal features having more than one metallic constituent by means of a single fill process.
It is yet another objective to provide a low temperature method for depositing metal into a patterned polymeric dielectric layer.
It is also an objective of the invention to provide atomic silicon to completely fill trenches of varying topography.